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ds05-11119-1e fujitsu semiconductor data sheet memory un-buffered 4 m 64 bit synchronous dynamic ram dimm MB8504S064AF-100/-84/-67 168-pin, 4 clock, 2-bank, based on 2 m 8 bit sdrams with spd n description the fujitsu mb8504s064af is a fully decoded, cmos synchronous dynamic random access memory (sdram) module consisting of sixteen mb81117822a devices which organized as two banks of 2 m 8 bits and a 2 k-bit serial eeprom on a 168-pin glass-epoxy substrate. the mb8504s064af features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb8504s064af is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. this module is ideally suited for workstations, pcs, laser printers, and other applications where a simple interface is needed. n product line & features parameter MB8504S064AF-100 mb8504s064af-84 mb8504s064af-67 clock frequency 100 mhz max. 84 mhz max. 67 mhz max. burst mode cycle time 10 ns max. (cl = 3) 15 ns max. (cl = 2) 12 ns max. (cl = 3) 17 ns max. (cl = 2) 15 ns max. (cl = 3) 20 ns max. (cl = 2) ras access time 54 ns max. 56 ns max. 60 ns max. cas access time 24 ns max. 26 ns max. 30 ns max. output valid from clock 8.5 ns max. (cl = 3) 9 ns max. (cl = 2) 8.5 ns max. (cl = 3) 9 ns max. (cl = 2) 9 ns max. (cl = 3) 10 ns max. (cl = 2) power dissipation burst mode 4752 mw max. 4464 mw max. 4176 mw max. power down mode 115.2 mw max. un-buffered 168-pin dimm socket type (lead pitch: 1.27 mm) conformed to jedec standard (4 clk) organization: 4,194,304 words 64 bits memory: mb81117822a (2 m 8, 2-bank) 16 pcs. 3.3 v 0.3 v supply voltage all input/output lvttl compatible 2048 refresh cycle every 32.8 ms auto and self refresh cke power down mode dqm byte masking (read/write) serial presence detect (spd) with serial eeprom module size: 1.0 (height) 5.25 (length) 0.157 (thick)
2 MB8504S064AF-100/-84/-67 n package plastic dimm package (mds-168p-p14) package and ordering information ?168-pin dimm, order as mb8504s064af- dg (dg = gold pad)
3 MB8504S064AF-100/-84/-67 n pin assignments pin no. signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v ss 29 dqmb 1 57 dq 18 85 v ss 113 dqmb 5 141 dq 50 2dq 0 30 cs 0 58 dq 19 86 dq 32 114 cs 1 142 dq 51 3dq 1 31 n.c. 59 v cc 87 dq 33 115 ras 143 v cc 4dq 2 32 v ss 60 dq 20 88 dq 34 116 v ss 144 dq 52 5dq 3 33 a 0 61 n.c. 89 dq 35 117 a 1 145 n.c. 6v cc 34 a 2 62 n.c. 90 v cc 118 a 3 146 n.c. 7dq 4 35 a 4 63 n.c. 91 dq 36 119 a 5 147 n.c. 8dq 5 36 a 6 64 v ss 92 dq 37 120 a 7 148 v ss 9dq 6 37 a 8 65 dq 21 93 dq 38 121 a 9 149 dq 53 10 dq 7 38 a 10 66 dq 22 94 dq 39 122 ba 0 150 dq 54 11 dq 8 39 n.c. 67 dq 23 95 dq 40 123 n.c. 151 dq 55 12 v ss 40 v cc 68 v ss 96 v ss 124 v cc 152 v ss 13 dq 9 41 v cc 69 dq 24 97 dq 41 125 clk 1 153 dq 56 14 dq 10 42 clk 0 70 dq 25 98 dq 42 126 n.c. 154 dq 57 15 dq 11 43 v ss 71 dq 26 99 dq 43 127 v ss 155 dq 58 16 dq 12 44 n.c. 72 dq 27 100 dq 44 128 cke 0 156 dq 59 17 dq 13 45 cs 2 73 v cc 101 dq 45 129 cs 3 157 v cc 18 v cc 46 dqmb 2 74 dq 28 102 v cc 130 dqmb 6 158 dq 60 19 dq 14 47 dqmb 3 75 dq 29 103 dq 46 131 dqmb 7 159 dq 61 20 dq 15 48 n.c. 76 dq 30 104 dq 47 132 n.c. 160 dq 62 21 n.c. 49 v cc 77 dq 31 105 n.c. 133 v cc 161 dq 63 22 n.c. 50 n.c. 78 v ss 106 n.c. 134 n.c. 162 v ss 23 v ss 51 n.c. 79 clk 2 107 v ss 135 n.c. 163 clk 3 24 n.c. 52 n.c. 80 n.c. 108 n.c. 136 n.c. 164 n.c. 25 n.c. 53 n.c. 81 n.c. 109 n.c. 137 n.c. 165 sa 0 26 v cc 54 v ss 82 sda 110 v cc 138 v ss 166 sa 1 27 we 55 dq 16 83 scl 111 cas 139 dq 48 167 sa 2 28 dqmb 0 56 dq 17 84 v cc 112 dqmb 4 140 dq 49 168 v cc
4 MB8504S064AF-100/-84/-67 n pin descriptions symbol i/o function symbol i/o function a 0 to a 10 , ba 0 i address input dq 0 to dq 63 i/o data input/data output ras i row address strobe v cc power supply (+3.3 v) cas i column address strobe v ss ground (0 v) we i write enable n.c. no connection dqmb 0 to dqmb 7 i data (dq) mask sa 0 to sa 2 i serial pd address input clk 0 to clk 3 i clock input scl i serial pd clock cke 0 i clock enable sda i/o serial pd address/data input/output cs 0 to cs 3 i chip select top view chip 0 chip 1 chip 7 1 84 plane 0 85 168 plane 1 25.40 mm 133.37 mm (mds-168p-p14) chip 2 chip 3 chip 6 chip 4 chip 5 chip 8 chip 9 chip 15 chip 10 chip 11 chip 14 chip 12 chip 13 10 94 11 95 40 124 41 125
5 MB8504S064AF-100/-84/-67 n serial-pd information note: any write operation must not be executed into the addresses of byte 0 to byte 127. some or all data stored into byte 0 to byte 127 may be broken. *1. byte 22: sdram device attributes *2. byte 63: checksum for byte 0 to 62 this byte is the checksum for bytes 0 through 62. when this byte is added to the sum of bytes 0 through 62, the resulting 8-bit value is 00h. byte function described hex value -100 -84 -67 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 61 62 63 64 to 98 99 to 127 128+ de?es number of bytes written into serial memory at module manufacture total number of bytes of spd memory device fundamental memory type number of row addresses number of column addresses number of module banks data width data width (continuation) interface type sdram cycle time (highest cas latency) sdram access from clock (highest cas latency) dimm con?uration type refresh rate/type primary sdram width error checking sdram width minimum clock delay for back to back random column addresses burst lengths supported number of banks on each sdram device cas latency cs latency write latency sdram module attributes sdram device attributes sdram cycle time (2nd. highest cas latency) sdram access from clock (2nd. highest cas latency) sdram cycle time (3rd. highest cas latency) sdram access from clock (3rd. highest cas latency) minimum row precharge time (t rp ) row activate to row activate minimum (t rrd ) ras to cas delay min. (t rcd ) minimum ras pulse width module bank density unused storage locations spd data revision code checksum for byte 0 to 62 manufacturers information: unused storage vendor speci? data: unused storage unused storage locations 128 byte 256 byte sdram 11 9 2 bank 64 bit +0 lvttl 10/12/15 ns 8.5/8.5/9 ns non-parity self, normal 8 0 1 cycle 1, 2, 4, 8, page 2 bank 2, 3 0 0 un-buffer *1 15/17/20 ns 9/9/10 ns no support no support 30/35/40 ns 30/30/30 ns 30/30/30 ns 60/65/70 ns 32 mbyte 0 *2 80h 08h 04h 0bh 09h 02h 40h 00h 01h a0h 85h 00h 80h 08h 00h 01h 8fh 02h 06h 01h 01h 00h 06h f0h 90h 00h 00h 1eh 1eh 1eh 3ch 08h 00h 00h b2h 00h 00h 80h 08h 04h 0bh 09h 02h 40h 00h 01h c0h 85h 00h 80h 08h 00h 01h 8fh 02h 06h 01h 01h 00h 06h ffh 90h 00h 00h 23h 1eh 1eh 41h 08h 00h 00h 79h 00h 00h 80h 08h 04h 0bh 09h 02h 40h 00h 01h f0h 90h 00h 80h 08h 00h 01h 8fh 02h 06h 01h 01h 00h 06h ffh a0h 00h 00h 28h 1eh 1eh 46h 08h 00h 00h 24h 00h 00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tbd tbd upper v cc tolerance lower v cc tolerance supported write 1 /read burst supported precharge all supported auto- precharge supported early ras precharge 00000110
6 MB8504S064AF-100/-84/-67 block diagram dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 add. ras cas we dqm 2 m 8 chip 0 cke cs clk dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 10 w dqmb 0 add. ras cas we dqm 2 m 8 chip 1 cke cs dqmb 4 add. ras cas we dqm 2 m 8 chip 2 cke cs clk dqmb 1 add. ras cas we dqm 2 m 8 chip 3 cke cs dqmb 5 clk 0 add. ras cas we dqm 2 m 8 chip 4 cke cs 10 w dqmb 2 add. ras cas we dqm 2 m 8 chip 5 cke cs add. ras cas we dqm 2 m 8 chip 6 cke cs clk add. ras cas we dqm 2 m 8 chip 7 cke cs dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 10 w cke 0 cke 1 cs 0 cs 1 clk clk a 0 to a 10 , ba 0 ras cas we serial eeprom sa 0 sa 1 sa 2 a 0 a 1 a 2 sda sda scl scl add. ras cas we dqm 2 m 8 chip 8 cke cs clk add. ras cas we dqm 2 m 8 chip12 cke cs add. ras cas we dqm 2 m 8 chip13 cke cs add. ras cas we dqm 2 m 8 chip 14 cke cs clk add. ras cas we dqm 2 m 8 chip 15 cke cs clk clk add. ras cas we dqm 2 m 8 chip 9 cke cs add. ras cas we dqm 2 m 8 chip 10 cke cs clk add. ras cas we dqm 2 m 8 chip 11 cke cs dqmb 6 dqmb 3 dqmb 7 clk clk clk clk clk clk cs 2 cs 3 clk 1 10 w 10 w 10 w clk 2 clk 3 v cc 10 k w
7 MB8504S064AF-100/-84/-67 n absolute maximum ratings (see warning) * : voltages referenced to v ss (= 0 v) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions *1. voltages referenced to v ss (= 0 v) *2. v il (min) = ?.5 v ac (pulse width 5 ns) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit min. max. supply voltage* v cc ?.5 +4.6 v input voltage* v in ?.5 +4.6 v output voltage* v out ?.5 +4.6 v storage temperature t stg ?5 +125 c power dissipation p d 10.4 w output current (d.c.) i out ?0 +50 ma parameter notes symbol value unit min. typ. max. supply voltage *1 v cc 3.0 3.3 3.6 v v ss 000v input high voltage, all inputs *1 v ih 2.0 v cc +0.5 v input low voltage, all inputs *1, 2 v il ?.5 0.8 v ambient temperature t a 0 +70 c
8 MB8504S064AF-100/-84/-67 n capacitance (v cc = +3.3 v, f = 1 mhz, t a = +25 c) parameter symbol value unit min. max. input capacitance a 0 to a 10 , ba 0 c in1 ?4pf ras , cas , we c in2 ?2pf cs 0 to cs 3 c in3 ?3pf cke 0 , cke 1 c in4 ?7pf clk 0 to clk 3 c in5 ?9pf dqmb 0 to dqmb 7 c in6 ?6pf scl c scl ?pf sa 0 , sa 1 , sa 2 c sa ?pf input/output capacitance sda c sda ?pf dq 0 to dq 63 c dq ?1pf
9 MB8504S064AF-100/-84/-67 n dc characteristics (at recommended operating conditions unless otherwise noted.) notes: *1. i cc depends on the output termination, load conditions, clock cycle rate and signal clock rate. the speci?d values are obtained with the output open and no termination register. *2. voltages referenced to v ss (= 0 v) *3. an initial pause (desl on nop) of 200 m s is required after power-on followed by a minimum of eight auto-refresh cycles. *4. values except i cc2p are for when one side of the double-sided module is in standby mode and the other side has two banks active in burst mode. *5. dc characteristics is the serial pd standby state (v in = gnd or v cc ). parameter notes symbol condition value unit min. max. operating current (average power supply current) *1 MB8504S064AF-100 i cc1s no burst; t ck = min t rc = min one bank active 920 ma mb8504s064af-84 880 ma mb8504s064af-67 840 ma MB8504S064AF-100 i cc1d no burst; t ck = min t rc = min all banks active 1280 ma mb8504s064af-84 1200 ma mb8504s064af-67 1120 ma precharge standby current (power supply current) *1 i cc2p cke = v il , t ck = min all banks idle ?2ma i cc2n cke = v ih , t ck = min all banks idle 480 ma active standby current (power supply current) *1 i cc3p cke = v il , t ck = min any bank active 480 ma i cc3n cke = v ih , t ck = min any bank active 640 ma burst mode current (average power supply current) *1 MB8504S064AF-100 i cc4 t ck = min 1320 ma mb8504s064af-84 1240 ma mb8504s064af-67 1160 ma auto-refresh current (average power supply current) *1 MB8504S064AF-100 i cc5 auto refresh t ck = min t rc = min t rrd = min 1360 ma mb8504s064af-84 1280 ma mb8504s064af-67 1200 ma self-refresh current (average power supply current) i cc6 cke = v il ?2ma input leakage current (all inputs) i i (l) 0 v v in v cc all other pins not under test = 0 v 3.0 v v cc 3.6 v ?0 80 m a output leakage current i o (l) output is disabled (hi-z) 0 v v out v cc 3.0 v v cc 3.6 v ?0 20 m a lvttl output high voltage *2 v oh i oh = ?.0 ma 2.4 v lvttl output low voltage *2 v ol i ol = +2.0 ma 0.4 v
10 MB8504S064AF-100/-84/-67 n ac characteristics (1) base characteristics (at recommended operating conditions unless otherwise noted.) no. parameter notes symbol mb8504s064af -100 mb8504s064af -84 mb8504s064af -67 unit min. max. min. max. min. max. 1 clock period cl = 3 t ck 10?2?5ns cl = 2 15?7?0ns 2 clock high time t ch 4??ns 3 clock low time t cl 4??ns 4cs set up time t sc 3??ns 5cs hold time t hc 1??ns 6 input set up time t si 3??ns 7 input hold time t hi 1??ns 8 data input set up time t sid 3??ns 9 data input hold time t hid 1??ns 10 output valid from clock (t clk = min) *1, *2 cl = 3 t ac 8.5 8.5 9 ns cl = 2 ??10 11 output in low-z t olz 3??ns 12 output in high-z *3 t ohz 3??ns 13 output hold time t oh 3??ns 14 time between refresh t ref 32.8 32.8 32.8 ms 15 transition time t t 0.5 2 0.5 2 0.5 2 ns 16 power down exit time t pde 3??ns
11 MB8504S064AF-100/-84/-67 (2) base values for clock count/latency (3) clock count formula (*8) (4) latency (the latency values on these parameters are ?ed regardless of clock period.) no. parameter notes symbol mb8504s064af -100 mb8504s064af -84 mb8504s064af -67 unit min. max. min. max. min.. max. 1 ras cycle time *4 t rc 90 100 110 ns 2 ras access time *5 t rac ?4?6?0ns 3 cas access time *6, *9 t cac ?4?6?0ns 4 ras precharge time t rp 30?5?0ns 5 ras active time t ras 60 100000 65 100000 70 100000 ns 6 ras to cas delay time *7 t rcd 30?0?0ns 7 write recovery time t wr 10?2?5ns 8 write precharge time t rwl 10?2?5ns 9 ras to cas bank active delay time t rrd 30?0?0ns no. parameter symbol mb8504s064af -100 mb8504s064af -84 mb8504s064af -67 unit 1 cke to clock disable i cke 1 1 1 cycle 2 dqm to output in high-z i dqz 2 2 2 cycle 3 dqm to input data delay i dqd 0 0 0 cycle 4 last output to write command delay i owd 2 2 2 cycle 5 write command to input data delay i dwd 0 0 0 cycle 6 precharge to output in high-z delay cl = 3 i roh 3 3 3 cycle cl = 2 2 2 2 cycle 7 mode register access to bank active (min) i mrd 2 2 2 cycle 8 cas to cas delay (min) i ccd 1 1 1 cycle 9 cas bank delay (min) i cbd 1 1 1 cycle clock 3 base value clock period (round off a whole number)
12 MB8504S064AF-100/-84/-67 notes: *1. assumes t rcd and t cac are satis?d. *2. t ac also speci?s the access time at burst mode except for ?st access. *3. speci?d where output buffer is no longer driven. *4. actual clock count of t rc (i rc ) will be sum of clock count of t ras (i ras ) and t rp (i rp ). *5. t rac is a reference value. maximum value is obtained from the sum of t rcd (min) and t cac (max). *6. assumes t rac and t ac are satis?d. *7. operation within the t rcd (min) ensures that t rac can be met; if t rcd is greater than the speci?d t rcd (min), access time is determined by t cac and t ac . *8. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *9. the i cac (cas latency: cl) is programmed by the mode register. *10. an initial pause (desl on nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. *11. 1.4 v or v ref is the reference level for measuring timing of signals. transition times are measured between v ih (min) and v il (max). *12. ac characteristics assume t t = 1 ns and 30 pf of capacitive load. *source: see mb811171822a data sheet for details on the electricals.
13 MB8504S064AF-100/-84/-67 n ac operating test condition (example of ac test load circuit) i/o z = 50 w 50 w 1.4 v 30 pf
14 MB8504S064AF-100/-84/-67 n serial presence detect(spd) function 1. pin descriptions scl (serial clock) scl input is used to clock all data input/output of spd sda (serial data) sda is a common pin used for all data input/output of spd. the sda pull-up resistor is required due to the open-drain output. sa 0 , sa 1 , sa 2 (address) address inputs are used to set the least signi?ant three bits of the eight bits slave address. the address inputs must be ?ed to select a particular module and the ?ed address of each module must be different each other. 2. spd operations clock and data convention data states on the sda can change only during sc l= low. sda state changes during scl = high are indicated start and stop conditions. refer to fig. 1 below. start condition all commands are preceded by a start condition, which is a transition of sda state from high to low when scl = high. spd will not respond to any command until this condition has been met. stop condition all read or write operation must be terminated by a stop condition, which is a transition of sda state from low to high when scl = high. the stop condition is also used to make the spd into the state of standby power mode after a read sequence. start fig. 1 ?start and stop conditions stop scl sda start = high to low transition of sda state when scl is high stop = low to high transition of sda state when scl is high
15 MB8504S064AF-100/-84/-67 acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will put the sda line to low in order to acknowledge that it received the eight bits of data. the spd will respond with an acknowledge when it received the start condition followed by slave address issued by master. in the read operation, the spd will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is issued by master, the spd will continue to transmit data. if an acknowledge is not detected, the spd will terminated further data transmissions. the master must then issue a stop condition to return the spd to the standby power mode. in the write operation, upon receipt of eight bits of data the spd will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. slave address addressing following a start condition, the master must output the eight bits slave address. the most signi?ant four bits of the slave address are device type identi?r. for the spd this is ?ed as 1010[b]. refer to the fig. 2 below. the next three signi?ant bits are used to select a particular device. a system could have up to eight spd devices ?amely up to eight modules?on the bus. the eight addresses for eight spd devices are de?ed by the state of the sa 0 , sa 1 and sa 2 inputs. the last bit of the slave address de?es the operation to be performed. when r/w bit is ?? a read operation is selected, when r/w bit is ?? a write operation is selected. following the start condition, the spd monitors the sda line comparing the slave address being transmitted with its slave address (device type and state of sa 0 , sa 1 , and sa 2 inputs). upon a correct compare the spd outputs an acknowledge on the sda line. depending on the state of the r/w bit, the spd will execute a read or write operation. 1 0 1 0 r/w sa 2 sa 1 sa 0 device type identifier device address fig. 2 ?slave address
16 MB8504S064AF-100/-84/-67 3. read operations current address read internally the spd contains an address counter that maintains the address of the last data accessed, incremented by one. therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). upon receipt of the slave address with the r/w bit = ?? the spd issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 3 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit = ?? the master must ?st perform a ?ummy write operation on the spd. the master issues the start condition, and the slave address followed by the word address. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/ w bit = ?? this will be followed by an acknowledge from the spd and then by the eight bits of data. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 4 for the sequence of address, acknowledge and data transfer. fig. 3 ?current address read s t o p data a c k slave address s t a r t bus activity : master sda line bus activity : spd fig. 4 ?random read s t o p data a c k slave address a c k a c k slave address word address s t a r t s t a r t bus activity : master sda line bus activity : spd
17 MB8504S064AF-100/-84/-67 sequential read sequential read can be initiated as either a current address read or random read. the ?st data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. the spd continues to output data for each acknowledge received. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 5 for the sequence of address, acknowledge and data transfer. the data output is sequential, with the data from address(n) followed by the data from address(n+1). the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 255), the counter ?olls over to address 0 and the spd continues to output data for each acknowledge received . 4. dc characteristics note: *1. referenced to v ss . parameter note symbol condition value unit min. max. input leakage current s ili 0 v v in v cc ?0 10 m a output leakage current s ilo 0 v v out v cc ?0 10 m a output low voltage *1 s vol i ol = 3.0 ma 0.4 v fig. 5 ?sequential read s t o p a c k a c k a c k data (n+x) data (n+2) data (n+1) data (n) slave address a c k bus activity : master sda line bus activity : spd
18 MB8504S064AF-100/-84/-67 5. ac characteristics no. parameter symbol value unit min. max. 1 scl clock frequency f scl 0 100 khz 2 noise suppression time constant at scl, sda inputs t i 100 ns 3 scl low to sda data out valid t aa 3.5 m s 4 time the bus must be free before a new transmission can start t buf 4.7 m s 5 start condition hold time t hd:sta 4.0 m s 6 clock low period t low 4.7 m s 7 clock high period t high 4.0 m s 8 start condition set up time t su:sta 4.7 m s 9 data in hold time t hd:dat 0 m s 10 data in set up time t su:dat 250 ns 11 sda and scl rise time t r ? m s 12 sda and scl fall time t f 300 ns 13 stop condition set up time t su:sto 4.7 m s 14 data out hold time t dh 100 ns 15 write cycle time t wr ?5ms t f t high t low t r t hd : dat t su : dat t su : sto t aa t dh t buf t hd : sta scl sda (input) sda (output) t su : sta fig. 6 ?timing waveform
19 MB8504S064AF-100/-84/-67 n package dimension 168-pin dual in-line memory module (case no.: mds-168p-p14) c 1996 fujitsu limited m168014sc-1-1 84 1 85 168 65.680.13(2.586.005) 66.680.13(2.625.005) c l 131.350.13(5.171.005) 133.350.13(5.250.005) 4.000.13 (.157.005) ?3.000.05 (?.118.002) 3.000.13 (.118.005) 25.400.13 (1.000.005) 3.170.13 (.125.005) 36.830.05 (1.450.002) 43.180.13(1.700.005) 11.430.05 (.450.002) c l 1.270.03 (.050.001) 54.610.05(2.150.002) 115.570.13(4.550.005) 127.350.10(5.014.004) pin no.1 index. .050 ?.003 +.004 ?0.08 +0.10 1.27 17.780.13 (.700.005) notches full r "a" "b" "c" 1.000.05 (.039.002) details of "c" part 3.25(.128) 3.00(.118) c l 2.54(.100)typ. 0.25(.010)max. details of "b" part 4.00(.157)min. 2.000.10(.079.004) 1.000.05(.039.002) 6.350.13 (.250.005) 3.25(.128) 3.00(.118) 2.000.10(.079.004) 1.000.05(.039.002) details of "a" part 4.00(.157)max. 3.00(.118)min. 6.350.13 (.250.005) dimension in mm (inches)
20 MB8504S064AF-100/-84/-67 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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